1. Field of the Invention
The present invention is generally related to a data access method of a semiconductor memory device in the case that a refresh operation is executed as an internal access operation which is independently carried out with respect to an external access operation, and also related to a semiconductor memory device. More specifically, the present invention is directed to a data access method of a semiconductor memory device, capable of effectively executing a refresh operation during an external access operation, or between successive external access operations, and also directed to a semiconductor device.
2. Description of Related Art
In volatile semiconductor memory devices which are typically known as dynamic random access memories (will be referred to as “DRAMs” hereinafter), refresh operations must be regularly carried out in order to maintain data stored in memory cells.
FIG. 14 indicates operating waveforms as to a so-called “self-refresh operation”, namely, a refresh operation which is automatically carried out every predetermined time period under stand-by state among general-purpose refresh operations in prior art. Symbol (I) of FIG. 14 shows a control operation executed in the case of an asynchronous type DRAM. In this control operation, for instance, a self-refresh operation is carried out in a CAS before RAS (will be referred to as a “CBR” hereinafter) refresh operation. As to an external control signal “/RAS” and another external control signal “/CAS”, a self-refresh operation is controlled in accordance with a signal transition sequence which is reversed with respect to the normal access operation. That is, the external control signal “/CAS” is transferred to a negative logic level before the external control signal “/RAS” is transferred to a negative logic level. The condition of the self-refresh operation is maintained under such a condition that both the external control signals “/RAS” and “/CAS” are at the negative logic levels. Also, symbol (II) of FIG. 14 shows a control operation executed in the case of a synchronous type DRAM (will be referred to as an “SDRAM” hereinafter). In this SDRAM control operation, a self-refresh operation is carried out by entering a command in synchronism with a clock signal “CLK.” The self-refresh operation is commenced in response to a start command “REF” of the refresh operation, and thereafter, the self-refresh condition is maintained. The self-refresh condition is ended in response to another command “EXIT.”
Within a time period of a self-refresh operation, an external access operation (for example, data is read/written) is not carried out (see symbol “III” of FIG. 14), but a refresh operation corresponding to an internal access operation is continued. Are fresh execution signal is outputted based upon a refresh-operation-start-request signal “REQ (I)” outputted in a predetermined refreshing time period, and thus, a refresh operation is sequentially carried out with respect to memory cell groups which are connected to word lines having predetermined addresses. FIG. 14 shows that word lines defined from an address “#0” up to an address “#N” are sequentially selected.
Within a self-refresh time period during which an external access operation (for example, data is read/written) is not executed, a refresh operation is intermittently carried out every predetermined time period. Conventionally, under such a circumstance, since a cycle time in a refresh operation is extended so as to improve a restore level of data into a memory cell, a refresh time period is prolonged, so that a current consumed during a self-refresh time period is tried to be reduced.
For instance, in such a semiconductor memory device described in Japanese Laid-Open Patent Publication No. 5-258562, this semiconductor memory device owns the self-refresh function capable of automatically and internally refreshing the memory cells. The semiconductor memory device to which time out is set is constituted by the time-out-initiating means (RAS), the time-out-terminating means (φSA), and also, the means for delaying the termination of the time out based upon the signal (φS) indicative of the self-refresh mode. As a result, upon receipt of the signal (φS) indicative of the self-refresh mode, the termination of the active time out may be delayed, as compared with that of the normal operation.
Also, as to such a semiconductor memory circuit disclosed in Japanese Laid-Open Patent Publication No. 2001-283586, the semiconductor memory circuit equipped with the refresh function used to restore the data held in the memory cell is constituted by employing the circuit system for switching the delay amounts of the signals in such a manner that while the CBR refresh time is defined as the reference time, the signal for defining the deactivation of the word line during the self-refresh time is delayed. As a result, while the semiconductor memory circuit owns the circuit system capable of switching the signal path for resetting the internal ROW-system signal in the self-refresh operation and the CBR refresh operation, the tRAS-time period is prolonged and the restore level is secured during the self-refresh operation.
In these measures, as indicated in FIG. 15, the cycle time during the self-refresh operation is extended, as compared with the time in either the normal operation or the CBR refresh operation in order to increase the amplification level of the bit line pair (namely, both “BL” and “/BL”), so that the restore level to the memory cell may be improved.
The above-described measures are executed so as to achieve an object of lowering of the current consumption during the self-refresh time period. In such a self-refresh time period, since an external access operation is not executed, high-speed operation is not required as to cycle time and access time. As a result, the above-described object may be achieved by conversely extending cycle time during a refresh operation.
On the other hand, very recently, as a result of such a fact that since portable appliances are popularized, functions required for these portable appliances are increased, semiconductor memory devices having larger memory capacities have been required instead of static random access memories (will be referred to as “SRAMs” hereinafter) which have been conventionally mounted on these portable appliances. Due to such a necessity that these semiconductor memory devices having the larger memory capacities should be packaged with limited spaces with realistic prices while using DRAM type memory cells having high integration and lower bit unit cost instead of SRAM type memory cells, DRAMs containing refresh functions have been utilized. These DRAMs are so-called “pseudo-SRAMs” which contain control operation related to such refresh operations specific to memory cells of DRAMs. Also, in response to future requirements as to high-speed memory operations, a so-termed “pseudo-SSRAM” technical idea may be realized, while this pseudo-SSRAM technical specification may be suitable to an external technical specification of a synchronous type SRAM (will be referred to as an “SSRAM” hereinafter).
Since either a pseudo-SRAM or a pseudo-SSRAM may own compatibility with respect to either an SRAM or an SSRAM in view of circuit operations thereof, in either the pseudo-SRAM or the pseudo-SSRAM, a refresh operation may be automatically carried out in arbitrary timing if necessary. As a consequence, both a refresh operation corresponding to an internal access operation, and normal read/write operations corresponding to an external access operation are independently carried out at arbitrary timing.
FIG. 16 shows conditions as to both an external access operation and a refresh operation of a pseudo-SRAM in the conventional technique. It should be understood that the refresh operation corresponding to the internal access operation is carried out independent from read/write operations corresponding to the external access operation. Symbol (I) of FIG. 16 shows a refresh cycle. With respect to a refresh-operation-start-request signal REQ (I), a refresh execution signal is outputted, so that a refresh operation is executed with respect to the address #0. Symbol (II) of FIG. 16 represents an external access cycle. In response to an external-operation-start-request signal REQ (O), an external access operation is carried out.
Symbol (III) of FIG. 16 represents such a case that the external-access-operation-start-request signal REQ (O) is in competition with the refresh-operation-start-request signal REQ (I). In this case, an adjustment between the external access operation, and the refresh operation is required. An access competition (1) corresponds to such a case that the refresh-operation-start-request signal REQ (I) is detected prior to the external-operation-start-request signal REQ (O). As to operation sequence in this case, the refresh operation for the address #1 is executed at a top priority, and subsequently, the external access operation is executed. A cycle time “tCE” is defined by both the refresh operation and the external access operation. An access competition (2) corresponds to such a case that the external-operation-start-request signal REQ (O) is detected prior to the refresh operation-start-request signal REQ (I). As to operation sequence in this case, the external access operation is executed at a top priority, and subsequently, the refresh operation for the address #2 is executed. A cycle time tCE is defined by both the refresh operation and the external access operation. An access competition (3) corresponds to such a case that both the refresh-operation-start-request signal REQ (I) and the external-operation-start-request signal REQ (O) are detected at the same time. The operation sequence of this case depends upon a control operation of a semiconductor memory device. However, generally speaking, such a control operation is carried out. That is, it is a top priority to avoid that data disappears by executing the refresh operation prior to the external access operation. Thus, the refresh operation for the address #3 is executed at a top priority, and subsequently, the external access operation is executed. A cycle time “tCE” is defined by both the refresh operation and the external access operation.
FIG. 17 indicates both input/output operations of data in an external access operation, and a differential amplification operation of a bit line pair (“BL” and “/BL”) in data restore operation in a refresh operation. As to each of operations when a refresh operation is performed (symbol (A) in FIG. 17), when a read operation is performed (symbol (B) in FIG. 17), and when a write operation is performed (symbol (C) in FIG. 17), FIG. 17 indicates temporal comparisons executed until memory cell data which has been read, or written into the bit line pair (“BL” and “/BL”) in conjunction with activation of a word line “WL” is amplified to such a voltage level higher than, or equal to a specified voltage level VH (MIN). It should be noted that as to a complementary bit line “/BL”, this level is lower than, or equal to VL (MIN). FIG. 17 shows temporal comparisons defined from activation of a sense amplifies activating signal “φSA” until the bit line pair (“BL” and “/BL”) reaches a specified voltage.
Prior to explanations as to FIG. 17, input/output paths of data from memory cells will now be briefly described with reference to FIG. 18. Memory cells “Ta” to “Td” are connected to the respective bit lines “/BL0”, “/BL1”, “BL0”, and “BL1.” Since either a word line “WL0” or another word line “WL1” is activated, storage charges which have been stored in these memory cells Ta to Td are again distributed into either the bit lines BL0 and BL1 or the bit lines /BL0 and /BL1. Thereafter, these distributed storage charges are differential-amplified in the bit line pair (BL0 and /BL0) and the bit line pair (BL1 and /BL1) by sense amplifiers “SA0” and “SA1.” The differential-amplified data are outputted via either column switches T01 and T02, or column switches T11 and T12 to data lines DB and /DB, and then are amplified by a read amplifier “RA”, and thereafter, the data amplified by this read amplifier RA is outputted from an input/output buffer “Buf” (Dout). Conversely, input data “Din” is amplified via the input/output buffer Buf by a write amplifier “WA”, and then, this amplified input data “Din” is stored in such a manner that the amplified input data are stored as charges from data lines DB and /DB via either the column switches T01 and T02 or the column switches T11 and T12, and also via either the bit lies BL0 and /BL0 or the bit lines BL1 and /BL1 into memory cells Ta to Td. Also, in the refresh operation, the charges which have been again distributed from the memory cells Ta to Td to either the bit lines BL0 and BL1 or the bit lines /BL0 and /BL1 by activating either the word line WL0 or the word line WL1 are differential-amplified by both the sense amplifiers SA0 and SA1, and thereafter, since either the word line WL0 or the word line WL1 is deactivated, the data is restored. In this case, since no data is inputted and/or outputted from an external circuit, either the column switches T01 and T02 or the column switches T11 and T12 are not brought into conductive states.
The activation of either the word line WL0 or another word line WL1 is carried out by that an activating signal “SET” derived from a row-system-activation control circuit “RCA” which receives an external-access-operation/refresh operation-start-request signal REQ (O)/(I)is entered in to a word decoder“WD.” Also, the activating signal SET is also entered into the sense amplifier signal circuit SC which outputs the sense amplifier activating signal φSA. Also, a deactivating signal “RST” which deactivates both the word line WL0 and WL1, and also the sense amplifier activating signal φSA is outputted by a deactivation timing circuit 100 after a predetermined delay time from the activating signal SET.
Also, control signals “ACL” and “/ACL”, complementary to each other, are outputted from a column system control circuit CC. The control signal ACL is decoded by the column switch signal circuit CS, and then, the column switch signal circuit CS outputs either a column switch signal “CL0” or another column switch signal “CL1” of either the column switches T01 and T02 or the column switches T11 and T12. On the other hand, while the complementary control signal “/ACL” controls PMOS transistors TP1 and TP2 which connects the data lines DB and /DB with a (½) VCC voltage supply line, the data lines DB and /DB are precharged to a (½) VCC voltage within a time period during which data is not inputted and outputted.
It should also be noted that in FIG. 18, the PMOS transistors TP1 and TP2 corresponding to the precharge elements of the data lines DB and /DB may be operated in another manner. That is to say, the control signal /ACL of the PMOS transistors TP1 and TP2 are continuously activated either during the refresh operation or during the read operation, so that the data line pair (DB and /DB) may be equalized to an arbitrary potential, or voltage amplitudes are limited. During the write operation, this control signal /ACL is deactivated, so that the data line pair (DB and /DB) may be set to the operating voltage of the write amplifier WA. Furthermore, the (½) VCC voltage may be substituted by an arbitrary voltage.
Referring back to FIG. 17, a comparison is made of respective time durations defined from the sense amplifier activating signal φSA until the bit line pair (BL and /BL) becomes the specified voltage levels VH(MIN) and VL(MIN) in the respective operation modes (symbols (A) to (C) shown in FIG. 17). Since the refresh operation (symbol (A) in FIG. 17) is directed to the restore operation with respect to the memory cell, either the column switches T01 and T02 or the column switches T11 and T12 are not brought into conductive states while the amplifying operations by the sense amplifiers SA0 and SA1 are carried out. As a consequence, while the amplifying operations by the sense amplifiers SA0 and SA1 are carried out, the data lines DB and /DB are not connected as loads, but the bit line pair (BL and /BL) is amplified up to the specified voltage for amplification time “of the refresh operation tRef.”
Within the read operation (symbol (B) sown in FIG. 17), either the column switches T01 and T02 or the column switches T11 and T12 are brought into conductive states by the column switch signal CL when the amplifying operations of the sense amplifiers SA0 and SA1 are being performed, and thus, read data are outputted to the data lines DB and /DB. At the connection time instant, since the data lines DB and /DB are precharged to the (½) VCC voltage, either the column switches T01 and T02 or the column switches T11 and T12 are brought into the conductive states, so that the bit line pair (BL and /BL) is disturbed thereby, and thus, the differential amplification level is retreated. It should be understood that even after either the column switches T01 and T02 or the column switches T11 and T12 are brought into non-conductive states, since the differential amplifications by the sense amplifiers SA0 and SA1 are continued, the bit line pair (BL and /BL) finally reaches the specified voltages. It should also be noted that since the bit line pair (BL and /BL) is disturbed while the column switches T01 and T02 or the column switches T11 and T12 are brought into the conductive states, the amplification time of the read operation “tRD” is prolonged, as compared with the above-described amplification time of the refresh operation “tRef.”
Within the write operation (symbol (C) shown in FIG. 17), either the column switches T01 and T02 or the column switches T11 and T12 are brought into the conductive states by the column switch signal CL when the amplifying operations of the sense amplifiers SA0 and SA1 are being carried out, so that data are written from the data lines DB /DB into the bit lines BL and /BL. In symbol (C) of FIG. 17, there is shown such a case that inverted data are written. In this case, the voltage levels of the bit line pair (BL and /BL), which are differential-amplified up to a half way of the voltage levels, must be inverted. The voltage levels of the bit line pair (BL and /BL) which have been inverted by a write amplifier “WA” and by bringing either the column switches T01 and T02 or the column switches T11 and T12 into the conductive states are differential-amplified by the sense amplifiers SA0 and SA1 even after either the column switches T01 and T02 or the column switches T11 and T12 are brought into the non-conductive states, and then, the differential-amplified levels reach the specified voltages. Since the amplified data must be inverted, amplification time of the write operation “tWT” is prolonged, as compared with the above-described amplification time of the read operation “tRD.”
In other words, the external access operation requires the longer amplification time than the amplification time required by the refresh operation. That is, in the refresh operation, only the row system operation is carried out without having the input/output operations of the data, and the amplifying operation is completed while the bit lines BL and /BL are employed as the main loads. In the external access operation, not only the row system operation but also the column system operation are carried out with having the input/output operations of the data, and while the data disturbance, or the data inversion is accepted, the amplifying operation is carried out by employing both the bit lines BL and /BL, and also the data lines DB and /DB as the main loads. A comparison of the amplification time among the respective operation modes is defined as follows: tRef<tRD<tWT. Since the cycle time tCE appeared on the operation is set in such a manner that these amplification time “tRef”, “tRD”, and “tWT” are fitted into this cycle time, timing involving the amplification time of the write operation tWT is set in the deactivation timing circuit 100, and thus, the cycle time tCE appeared on the operation may be determined.
However, in the prior art, while the longest amplification time “tWT” required when the inverted data is written is employed as the reference time, the deactivating signal RST is produced by the deactivation timing circuit 100. As a result, in the read operation as well as the refresh operation, in which the voltage levels of the bit line pairs (BL and /BL) can be amplified within shorter amplification time than that of the above-explained write operation, such an amplification time longer than the necessary amplification time is secured. In other words, in the read operation, such a time defined by (tWT-tRD) is continuously added even after the differential amplifying operation is accomplished. Also, in the refresh operation, such a time defined by (tWT-tRef) is always added even after the differential-amplifying operation is accomplished.
As a consequence, as to such a case that the external-access-operation-start-request signal REQ(O) is in competition with the refresh-operation-start-request signal REQ(I) (see symbol (III) of FIG. 16), as illustrated in the access competition (1) and (3), when the refresh operation is executed prior to the external access operation, unnecessary time longer than, or equal to an ability value is added to the amplification time of the refresh operation “tRef” required in the refresh operation. As a result, the access time “tCE” with respect to the external access operation (for example, read operation and write operation) which is executed subsequent to this refresh operation would become longer than, or equal to the ability value. Therefore, there is such a problem that the access time “tCE” cannot be achived in a high speed.
Also, due to a similar reason, the cycle time “tCE” cannot be shortened. That is to say, in the case that a refresh operation is controlled on the side of such a system which controls a semiconductor memory device, the system cannot shorten a time duration defined from a commencement of the refresh operation of the semiconductor memory device up to an end of this refresh operation, which are executed by either a produced refresh signal or a produced refresh command, so that a busy rate of the semiconductor memory device in the system cannot be lowered.
Because of these difficulties, when a system is constituted, there are such problems that both a data-occupation rate and a data-transfer rate in a data bus cannot be increased.
Also, as to such a case that the accesses compete with each other (see symbol (III) of FIG. 16), as shown as the access competition (2), when the external access operation is carried out prior to the refresh operation, longer time than, or equal to the ability value is required for the amplification time “tRef” required for the refresh operation which is executed subsequent to this external access operation. As a result, the cycle time “tCE” cannot be shortened. In the case that a system is constituted, there is another problem that both a data-occupation rate and a data-transfer rate in a data bus cannot be increased.
Also, as to the read operation among the external access operations, since the longer time (namely, tWT-tRD) than, or equal to the ability value is required for the amplification time “tRD”, this fact impedes shortening of both the access time and the cycle time in a similar manner.
Also, in such a case that while no access competition occurs, either the refresh operation or the external access operation is solely carried out (see symbols (I) and (II) of FIG. 16), longer time than, or equal to the ability value is necessarily required in either the refresh operation or the read operation, the cycle time “tCE” cannot be shortened. When a system is constituted, both a data-occupation rate and a data-transfer rate in a data bus cannot be increased, resulting in another problem.
Considering now such cases that a so-called “pseudo-SRAM” and a so-termed “pseudo-SSRAM” are realized in a near future, or a semiconductor memory device which requires a new high-speed access operation specification is realized, otherwise, another semiconductor memory device is realized in which a high data-occupation rate specification is required in a data bus when a system is constituted, the following problems may possibly occur in the prior art. That is, when are fresh operation is embedded with in an external access operation, or between successive external access operations, or when a refresh operation is set between successive external access operations, the conventional data access methods cannot be properly applied thereto.